1. Field of the Invention
The present invention relates to a method of evaluating thermal treatment that is capable of conveniently evaluating with high precision the metal contamination from a thermal treatment process in the process of manufacturing a semiconductor wafer; and a method of manufacturing a semiconductor wafer capable of providing a semiconductor wafer with less contamination by metals from a thermal treatment process.
2. Discussion of the Background
Impurities in semiconductor wafers can compromise device characteristics and greatly affect device manufacturing yields. Among such impurities, metal impurities readily diffuse into the interior of wafers during various thermal treatment processes such as oxidation, diffusion, and epitaxial growth during the process of manufacturing a wafer. They can potentially cause deposits, dislocation, oxidation-induced stacking faults (OSF), and other crystal defects; shorten the minority carrier lifetime; increase current leaks; and reduce the breakdown voltage of oxide films, and the like. Thus, to decrease metal contamination in thermal treatment processes, prior to thermally treating the actual product, a wafer for evaluating the level of process contamination of the heating furnace being employed can be used for test evaluation. Once contamination has been reduced based on the evaluation value, the actual product is thermally treated. Evaluation wafers are also sometimes introduced into heating furnaces as part of daily management in evaluation and control.
Conventionally, the surface Photo Voltage (SPV) method and lifetime method have been employed to evaluate the metal contamination of such evaluation wafers. However, although these methods can permit convenient evaluation, the only metal that can be quantitatively evaluated is iron. Metal impurities such as nickel and copper that can also negatively affect semiconductor wafer characteristics cannot be efficiently quantified by the SPV method.
Accordingly, the present inventors proposed a wafer for evaluating thermal treatment processes in which a gettering layer trapping metal impurities is provided on a prescribed silicon wafer (see Japanese Unexamined Patent Publication (KOKAI) Heisei No. 10-223713, which is expressly incorporated herein by reference in its entirety) as a wafer for evaluating metal contamination such as copper and nickel in thermal treatment processes.
The wafer described in Japanese Unexamined Patent Publication (KOKAI) Heisei No. 10-223713 permits the highly sensitive evaluation of metal impurities that are difficult to evaluate by the conventional SPV and lifetime methods, and the like. However, since the above-cited method traps metal impurities in a layer, it becomes necessary to dissolve the gettering layer and an SiO2 layer to analyze the metal impurities.